1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly relates to a vertical transistor using silicon pillars and a manufacturing method thereof.
2. Description of Related Art
Improvement in integration of semiconductor devices has so far been achieved by mainly downscaling transistors. However, the downscaling of transistors has almost reached its limit, and if transistor sizes are further decreased, the transistors have a risk of being unable to operate correctly due to a short-channel effect and the like.
To fundamentally solve this problem, there is proposed a method of three-dimensionally processing a semiconductor substrate, thereby three-dimensionally forming a transistor. Particularly, a three-dimensional transistor using, for a channel, silicon pillars perpendicularly extended with respect to a main surface of the semiconductor substrate has an advantage of a smaller occupied area and capable of obtaining a large drain current by complete depletion. Further, this transistor can achieve the closest layout of 4F2 (see Japanese Patent Application Laid-open Nos. 2007-123415 and 2008-288391).
In the three-dimensional transistor described above, a conductive layer is formed on an upper part of the silicon pillars. This conductive layer is, for example, a diffusion layer that becomes either a source or a drain of the transistor. An upper part of the conductive layer is connected to a contact plug, and is further connected to an upper wiring layer and the like via this contact plug.
The conductive layer is formed in self-alignment by using a silicon-nitride film mask used to form silicon pillars, as disclosed in Japanese Patent Application Laid-open No. 2008-288391, for example. That is, to form a three-dimensional transistor, silicon pillars are first formed by dry etching by using a silicon-nitride film mask, and an interlayer dielectric film is deposited next on the entire surface of a substrate. A surface of the interlayer dielectric film is flattened to expose an upper end of the silicon-nitride film mask by using a CMP (Chemical Mechanical Polishing) method. The silicon-nitride film mask is removed by dry etching or wet etching. As a result, a through-hole is formed in the interlayer dielectric film, and thus a conductive material is embedded into the through-holes, thereby forming the conductive layer.
According to the forming method of such a conductive layer, an area and position of a lower surface of the conductive layer match an area and position of an upper surface of the silicon pillars, respectively. Therefore, a contact resistance between the conductive layer and the silicon pillars is minimized. On the other hand, however, the forming method described above has a problem that a position margin (a contact margin) of a contact plug on the conductive layer becomes small. That is, according to the forming method, while silicon pillars are very thin in a highly-integrated semiconductor device, a thickness of the conductive layer cannot be larger than that of the silicon pillars, because the conductive layer is formed by embedding a conductive material into the through-hole formed by removing the silicon-nitride film mask. Accordingly, an area of the upper surface of the conductive layer becomes very small, and a contact margin of the contact plug on the conductive layer becomes small.